The present invention relates to a ferroelectric memory device. More particularly, the present invention relates to an improvement for processing the latest command when a write (program) and/or read command competes within a given period of time.
A cross-point type ferroelectric memory device in which only one ferroelectric capacitor is disposed in one memory cell has a program cycle and a read cycle of the same type as other memory devices such as an SRAM or DRAM.
In the SRAM or DRAM, new program data can be written in the middle of writing the program data. In the case where a program request occurs in the middle of the read cycle, the read cycle can be immediately changed to the program cycle.
The cross-point type ferroelectric memory device stores data by using hysteresis characteristics of the ferroelectric capacitor, differing from the SRAM or DRAM. Therefore, each of the program cycle and the read cycle includes a data “0” write period and data “1” write period, and substantially includes two steps (details are described later). Therefore, the cross-point type ferroelectric memory device may be synchronous in which a request or a change in program data is not accepted after the address of the selected memory cell has been designated and the program cycle or the read cycle has started.
In the synchronous ferroelectric memory device, a change to the program cycle is not accepted in the middle of the read cycle, and a change in program data is not accepted in the middle of the program cycle.
However, if only the cross-point type ferroelectric memory device is synchronous, the specification completely differs from that of the SRAM or DRAM. This causes inconvenience to the user.